1. Field of the Invention
The present invention relates to a semiconductor random access memory device. More particularly, this invention relates to a structure forming load resistances which are used in a memory cell.
A static random access memory (hereinafter, "SRAM") device comprises a plurality of memory cells. Each cell comprises a pair of inverters which include a field effect transistor (hereinafter, "FET") and its load. Generally, FETs or resistors are used for the load of the inverter. However, in recent high packing density memory device technology, resistors are becoming the main current for the load of the inverter since they can be formed over the FET which uses them as the load. Accordingly, decreasing the area of the unit cell and increasing the packing density of the memory cells in the device can be achieved.
2. Description of the Relevant Art
An exemplary configuration of a resistance loaded memory cell is shown in FIGS. 1(a) and (b). FIG. 1(a) is a schematic plan view illustrating an arrangement of electrodes and wirings of a memory cell pair. The left and right halves of FIG. 1(a) show a standard memory cell. FIG. 1(b) is a schematic cross-sectional view of the device taken in the direction of arrow X--X shown in FIG. 1(a). In FIG. 1(a), reference characters S and D designate source and drain regions of the FETs, respectively. Gate electrodes G of inverter FETs Q11, Q12, Q21, Q22 run in a horizontal direction between the source region S and drain region D in FIG. 1(a). Although gate electrodes G cannot be seen in FIG. 1(a), they can be seen in FIG. 1(b). Over the gate electrodes G, load resistors R11, R12, R21 and R22 are formed and separated from the gate electrodes G by an insulation layer 8. One end of each load resistance is connected to a respective gate electrode G through a respective gate contact hole 2. Field oxide layers 3 separate the devices from each other. The gate electrodes G are formed over respective gate oxide layers 4.
In FIG. 1(b), the source and drain regions of the FETs Q12 and Q22 cannot be seen since the cross-section is taken at a plane cutting the device just along the gate G. However, a typical cross-section of the FET can be seen at transfer transistors T11 and T21 which are located on both sides. The gates of these transfer transistors are respectively coupled to word lines WL1 and WL2, and their drains D are connected to bit lines (not shown) through drain contact holes 5 to convey the memory stored in the cell to an outer circuit. Respective portions of the word lines WL1 and WL2 crossing the transfer transistors T11, T12, T21 and T22 become their respective gate electrodes, as shown in the FIGS. 1(a) and (b). A voltage source line Vss is formed in the substrate 7 by diffusion and is buried between the field oxide layers 3. Another source line Vcc, as well as resistors, are formed over the surface of the insulation layer 8. The resistors R and Vcc lines shown in FIG. 1(a) are formed and patterned at the same time in similar fabrication steps.
An equivalent circuit diagram of the device of FIGS. 1(a) and (b) is shown in FIG. 2. The upper and lower halves of the circuit represent a unit memory cell corresponding to the left and right halves of FIG. 1(a), respectively. Each unit cell is composed of a pair of inverters forming a flip-flop circuit. For example, each memory cell includes four FETs Q11, Q12, T11 and T12, and two load resistors R11, R12. When a word line WL1 is selected, for example, the transfer transistor T11 or T12 conveys the state information that Q11 or Q12 high level to a sense amplifier (not shown) via the bit lines BL or BL in order to have the memory read out.
As can be seen in FIGS. 1(a) and 1(b), the load resistors (R11, etc.) of the memory cell can be fabricated over the inverter FETs (Q11, Q12, etc.). Thus, the area of the unit cell can be made smaller when compared to a circuit which uses FETs as the load of the inverters. This is the main reason that recent SRAM technology uses a resistance load for the flip-flop circuits. However, as the packing density increases, the problems hereinafter described become apparent.
In order to make the packing density as high as possible, the size of the unit cell is desirably made to be as small as possible, while simultaneously making the value of the resistance of the load resistor as high as possible since high resistance reduces power consumption. However, the size of the memory cells having a structure like FIG. 1 is practically limited by the fabrication technique of the load resistance, but the size of the transistors still have room for reduction.
As an example, the resistance of the load resistors is required to be about 10.sup.12 Ohms, and the current running through the resistance at 5 volts is approximately a few pico amperes. A material actually used for fabricating such a high resistance for a semiconductor device is polysilicon (polycrystalline silicon). The size of the load resistor used for a 1M bit SRAM, for example, becomes about 1 .mu.m wide, 3 .mu.m long and 2,000 .ANG. thick. From this size, the area occupied by the FET can be further reduced by photolithography, but the length of the load resistor cannot be reduced for reasons hereinafter described.
Generally, if resistance per unit length of the load resistors is increased, the size of the resistor can be decreased. In order to increase the resistance, however, the resistivity of the polysilicon must be increased, the thickness and the width of the resistor must be decreased, or the length of the resistor must be increased. However, there is a limit as to how much the resistivity of the polysilicon can be increased because there is a limitation as to how much the impurity concentration in the polysilicon can be reduced due to purity limitations of the material.
The thickness of the resistor also cannot be reduced very much due to the design of the device. As can be seen in FIGS. 1(a) and (b), the polysilicon layer 6 is used for load resistors R11, etc. Similarly, the same polysilicon layer 6 is used for fabricating the Vcc line of which the desired resistance is to be as low as possible. In order to decrease the resistance of the Vcc line, the portion of the Vcc line of the polysilicon layer 6 is ion-implanted in order to increase the conductivity. However, the conductivity of a thin polysilicon layer cannot be sufficiently increased because too much high doping of ion implantation causes a migration or diffusion of impurities in the lateral direction from the Vcc line. This causes a decrease in the resistance of the load resistor which is connected to the Vcc line. Therefore, a length of 3 .mu.m, for example, for the load resistor is necessary.
Further, though it is not shown in the figures, some other portion of the polysilicon layer 6 is patterned in various ways and utilized for fabricating some other parts of the device, such as, a fuse element which is inevitable for such a high density memory device for increasing the yield of the production. A protection circuit for protecting the device from unexpected high voltage surge is also fabricated using the same polysilicon layer 6. These devices all require high conductivity for the polysilicon layer 6. Thus, a thicker polysilicon layer is desirable for these parts.
The width of the resistor, as well as the size of other elemental devices, may be decreased by photolithography in order for the length of the load resistor to be decreased. However, there is another difficulty which arises; namely, a resistor having a very high resistance value requiring increased length. As previously discussed, the values of the resistance of the load resistor is 10.sup.12 Ohms with a 3 .mu.m length. However, having too short a length with high resistance causes instability due to surface instability and impurity diffusion. In the case of the resistance loaded cell shown in FIGS. 1(a) and (b), both sides of the load resistor contact high impurity regions, the Vcc line and the gate electrode. The impurities, especially those which are doped in the Vcc line, cause diffusion into the load resistor and decrease the effective length of the resistor.
It will be understood from FIG. 1(a) that the length of the resistor is already designed to the maximum length allowable in a unit cell. The resistors are extended over their full lengths between the Vcc line and the gate contact holes 2 which are located at another end of the inverter transistor Q. A further increase in the length causes an unnecessary elongation of the transistor Q; thereby, decreasing the packing density. Therefore, in order to fabricate a memory device having a further increased memory size, an increase in the size of the memory device is indispensable.
Efforts to increase the packing density in large scale integrated circuit (hereinafter, "LSI") are continuing in every field of semiconductor technology, especially in photolithographic technology. Even though photolithography is improved and the patterns of elemental devices are made smaller, the size of the SRAM is limited by the length of the load resistors for the reasons set forth above.
If the length of the load resistor from the drain of the inverter FET to the VCC line, hence the resistance of the load resistor, can be increased by extending it over the adjacent unit cell, a higher packing density can be achieved, because there is still sufficient room in the size of the inverter FET's to be reduced in size.